Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers
Daniel Etiemble *
LISN, Paris Saclay University, Gif sur Yvette, France.
Ramzi A. Jaber
Electrical and Electronic Engineering Department, Libanese University, Lebanon.
*Author to whom correspondence should be addressed.
Abstract
The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.
Keywords: CNTFET, ternary counters, wallace trees, combinational multipliers